Semiconductor device with terminals, and method of manufacturing the same

ABSTRACT

A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the closest solder balls of adjacent semiconductor chips becomes “n” times (“n” is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to a semiconductor device with a pluralityof terminals and to a method of manufacturing the device.

[0003] 2. Description of the Background Art

[0004] In association with recent miniaturization of a package, asemiconductor of ball grid array (BGA) type or land grid (LGA) type, inwhich external electrodes are arranged in a matrix pattern on the entireback surface of a substrate, has become pervasive.

[0005] A conventional semiconductor device and a method of manufacturingthe device will be described hereinbelow by reference to FIGS. 9 through17.

[0006]FIG. 9 is a view showing a front surface of a conventionalsemiconductor device; FIG. 10 is a cross-sectional view of thesemiconductor device shown in FIG. 9; FIG. 11 is a view showing the backsurface of the semiconductor device shown in FIG. 9; FIG. 12 is aperspective view showing an interior of a resin-sealed section shown inFIG. 9; FIG. 13 is a cross-sectional view of the resin-sealed sectiontaken along line b-b shown in FIG. 12; FIG. 14 is a view showing areasof the resin-sealed section to be sliced; FIG. 15 is an enlarged view ofareas on the back side of the semiconductor device to be sliced; FIG. 16is a cross-sectional view of sliced semiconductor devices; and FIG. 17is a cross-sectional view of a neighborhood of a solder ball shown inFIG. 16.

[0007] In FIGS. 9 through 17, reference numeral 1 designates a substratefor manufacturing semiconductor devices; 2 designates a resin-sealedsection; 3 designates solder balls; 4 designates a semiconductor chip; 5designates a wire; 6 designates an area to be sliced; 8 designates apackage; and 9 designates a land.

[0008] First, a conventional semiconductor device will be described.

[0009] As shown in FIGS. 9 and 10, a plurality of resin-sealed sections2 are formed on the surface of a substrate 1. As shown in FIG. 11, aplurality of solder balls 3 are formed on the back surface of thesubstrate 1 so as to correspond to the respective resin-sealed sections2. Specifically, as shown in FIG. 17, the solder balls 3 are formed onthe back surface of the substrate 1 via corresponding lands 9.

[0010] As shown in FIGS. 12 and 13, a plurality of semiconductor chips 4electrically connected to the substrate 1 by means of wires 5 areprovided in the resin-sealed sections 2.

[0011] As shown in FIGS. 14 through 16, an area to be sliced(hereinafter called a “slice area”) 6 is provided in each of theresin-sealed sections 2 located in a position between the adjacentsemiconductor chips 4 (or packages 8).

[0012] As shown in FIGS. 15 and 16, the plurality of solder balls 3,which serve as terminals for external electrodes, are provided on eachof the semiconductor chips 4 (or the packages 8) at uniform pitches Bof, e.g., 0.8 mm. An interval C between the closest solder balls 3 ofthe adjacent packages 8 (i.e., a package-to-package pitch) is a sum of adesired package size and the width of the slice area 6. For instance, ina case where a package size is 8 mm×8 mm and the width of the slice area6 is 0.35 mm, the package-to-package pitch C is 8.35 mm.

[0013] Next, there will now be described a method of manufacturing theabove-mentioned semiconductor device.

[0014] First, the plurality of semiconductor chips 4 are mounted on thesurface of the substrate 1. The substrate 1 and the semiconductor chips4 are electrically connected by use of the wires 5.

[0015] Next, the plurality of semiconductor chips 4 are collectivelysealed with resin, thus forming the resin-sealed sections 2.

[0016] Further, the lands 9 to be used for mounting solder balls areformed on the back surface of the substrate 1. The solder balls 3 areformed on the lands 9. Here, in the case of a semiconductor device ofLGA, formation of the solder balls 3 is obviated.

[0017] The resin-sealed sections 2, which have been collectively molded,are sliced along the cut areas 6 by means of a dicing saw, whereby theresin-sealed sections 2 are divided into a plurality of packages(semiconductor devices) 8.

[0018] Each of the packages 8 is subjected to an electrical test.

[0019] As mentioned above, when each of the packages 8 is subjected toan electrical test, a test tool such as a test contact pin must beprepared every time a package size is different. Therefore, cost of thetest tool is too high.

[0020] Further, no electrical test can be carried out during a period inwhich a test tool is replaced with another test tool, thereby resultingin inefficient conduction of an electrical test; that is, occurrence ofso-called package switching loss.

[0021] When a package is miniaturized to an extent to be called achip-scale package (CSP), a resultant package becomes too small orlightweight. Such packages will fall during the course of a test ortransport.

[0022] A method effective for solving the problem is to simultaneouslysubject the plurality of semiconductor chips 4 to a test while thesemiconductor chips 4 (or packages 8) are sliced into pieces orcollectively sealed with resin on the substrate 1.

[0023] However, a package size has already been determined by astandardization institution, such as a Japanese Electronics andInformation Technology Industries Associations). The interval C betweenthe closest solder balls 3 of the adjacent packages 8 (i.e., thepackage-to-package pitch C) is not necessarily an integral multiple ofthe interval B between the solder balls 3 in the package 8 (i.e., a ballpitch). Therefore, even in the case of a package of same size, a testtool must be prepared every time the intervals B and C are changed.Thus, costs for the tool cannot be curtailed.

[0024] Moreover, when packages of different sizes are manufactured, testtools for the respective packages must be prepared, thereby hinderingcurtailment of costs for the tools.

[0025] Accordingly, since commonality cannot be achieved in connectionwith positions of terminals (e.g., solder balls) 3 on the back side ofthe substrate 1, a test tool must be prepared every time the interval Cbetween the solder balls C of the adjacent packages 8 or a package sizehas become changed. For this reason, costs for the test tool cannot bediminished.

[0026] A necessity for replacement of test tools entails occurrence ofso-called package switching loss.

SUMMARY OF THE INVENTION

[0027] The present invention has been conceived to solve thepreviously-mentioned problems and a general object of the presentinvention is to provide a novel and useful semiconductor device, and isto provide a novel and useful method of manufacturing the semiconductordevice.

[0028] A more specific object of the present invention is to curtailcosts for a test tool used for electrical test of semiconductor devicesby establishing commonality in positions of terminals of semiconductordevices.

[0029] The above object of the present invention is attained by afollowing semiconductor device and a following method of manufacturing asemiconductor device.

[0030] According to one aspect of the present invention, thesemiconductor device comprises a plurality of semiconductor chipsmounted on a surface of a substrate. The plurality of semiconductorchips is collectively sealed with sealing resin. A plurality ofterminals is formed on a back surface of the substrate, wherein aninterval between the closest terminals of the adjacent semiconductorchips is an integral multiple of the interval between the terminals inthe semiconductor chip.

[0031] According to another aspect of the present invention, in themethod of manufacturing a semiconductor device, a plurality ofsemiconductor chips is mounted on a surface of a substrate. Theplurality of semiconductor chips is collectively sealed with resin. Aplurality of terminals is formed on a back surface of the substrate suchthat an interval between the closest terminals of the adjacentsemiconductor chips is an integral multiple of the interval between theterminals in the semiconductor chip. The plurality of semiconductorchips is subjected to an electrical test. The resin and the substrateare sliced, thereby breaking the semiconductor chips into pieces.

[0032] Other objects and further features of the present invention willbe apparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033]FIG. 1 is a view showing a surface of a semiconductor deviceaccording to an embodiment of the present invention;

[0034]FIG. 2 is a cross-sectional view of the semiconductor device shownin FIG. 1;

[0035]FIG. 3 is a view showing a back surface of the semiconductordevice shown in FIG. 1;

[0036]FIG. 4 is a perspective view showing an interior of a resin-sealedsection shown in FIG. 1;

[0037]FIG. 5 is a cross-sectional view of the resin-sealed section takenalong a-a shown in FIG. 4;

[0038]FIG. 6 is a view showing areas of the resin-sealed section to besliced;

[0039]FIG. 7 is an enlarged view of the sliced section on the backsurface of the semiconductor device;

[0040]FIG. 8 is a cross-sectional view of the sliced semiconductordevice;

[0041]FIG. 9 is a view showing a front surface of a conventionalsemiconductor device;

[0042]FIG. 10 is a cross-sectional view of the semiconductor deviceshown in FIG. 9;

[0043]FIG. 11 is a view showing the back surface of the semiconductordevice shown in FIG. 9;

[0044]FIG. 12 is a perspective view showing an interior of aresin-sealed section shown in FIG. 9;

[0045]FIG. 13 is a cross-sectional view of the resin-sealed sectiontaken along line b-b shown in FIG. 12;

[0046]FIG. 14 is a view showing areas of the resin-sealed section to besliced;

[0047]FIG. 15 is an enlarged view of areas on the back side of thesemiconductor device to be sliced;

[0048]FIG. 16 is a cross-sectional view of sliced semiconductor devices;and

[0049]FIG. 17 is a cross-sectional view of a neighborhood of a solderball shown in FIG. 16.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0050] In the following, principles and embodiments of the presentinvention will be described with reference to the accompanying drawings.The members and steps that are common to some of the drawings are giventhe same reference numerals and redundant descriptions therefore may beomitted.

[0051] By reference to FIGS. 1 through 8, a semiconductor deviceaccording to an embodiment of the invention and a method ofmanufacturing the semiconductor device will be described. Here, thepresent embodiment describes an example in which a BGA substrate is usedas a substrate for use in manufacturing a semiconductor device.

[0052]FIG. 1 is a view showing a surface of a semiconductor deviceaccording to an embodiment; FIG. 2 is a cross-sectional view of thesemiconductor device shown in FIG. 1; FIG. 3 is a view showing a backsurface of the semiconductor device shown in FIG. 1; FIG. 4 is aperspective view showing an interior of a resin-sealed section shown inFIG. 1; FIG. 5 is a cross-sectional view of the resin-sealed sectiontaken along a-a shown in FIG. 4; FIG. 6 is a view showing areas of theresin-sealed section to be sliced; FIG. 7 is an enlarged view of thesliced section on the back surface of the semiconductor device; and FIG.8 is across-sectional view of the sliced semiconductor device.

[0053] In FIGS. 1 through 8, reference numeral 1 designates a substratefor use in manufacturing a semiconductor device (hereinafter referred toas a “substrate”); 2 designates resin-sealed sections; 3 designates asolder ball (terminal); 4 designates a semiconductor chip; 5 designatesa wire; 6 designates an area to be sliced (hereinafter referred to as a“slice area”); 7 designates a residual remainder; 8 designates a package(semiconductor device); and 11 designates a test contact pin.

[0054] First, a semiconductor device of the embodiment will bedescribed.

[0055] As shown in FIGS. 1 and 2, a plurality of resin-sealed sections 2are formed on the surface of the substrate 1. Further, as shown in FIGS.4 and 5, a plurality of semiconductor chips 4 electrically connected tothe substrate 1 by means of wires 5 are provided in the resin sealedsections 2.

[0056] As shown in FIGS. 3 and 5, a plurality of solder balls 3 servingas external electrode terminals are formed on the back surface of thesubstrate 1 so as to correspond to the semiconductor chips 4 provided inthe resin-sealed sections 2. Here, the solder balls 3 are arranged suchthat an interval A between the closest solder balls 3 of the adjacentsemiconductor chips 4 (or the adjacent packages 8) becomes “n” times(where “n” is an integer greater than 1) an interval B between thesolder balls 3 provided in one semiconductor chip 4 (or one package 8).For instance, a package size is 0.8 mm×0.8 mm, and the interval Aassumes a value of 9.6 mm (=0.8 mm×12), and the interval B assumes avalue of 0.8 mm. Each of the solder balls 3 is formed on the backsurface of the substrate 1 through a land (9) electrically connected tothe semiconductor chip 4 (see FIG. 17). The value of “n” is usually setwithin a range of 2 to 20. In short, the interval A is set so as tobecome two to twenty times the interval B.

[0057] As shown in FIG. 5, the test contact pins 11 are arranged in agrid pattern at an interval identical with the interval B (e.g., 0.8 mm)between the solder balls 3. A semiconductor device is subjected to anelectrical test through use of the test contact pins 11 (which will bedescribed later).

[0058] As shown in FIGS. 6 through 8, two slice areas 6 to be sliced bya dicing saw are formed between the adjacent semiconductor chips 4 inthe resin-sealed section 2 and on the substrate 1. An area definedbetween the two slice areas 6; that is, a space between thesemiconductor chips 4 (or packages 8), corresponds to the residualremainder 7. The size of the residual remainder 7 changes in accordancewith a desired package size. In other words, a desired package isobtained by changing the size of the residual remainder 7. For instance,in the case of the foregoing package size, the width of the slice area 6assumes a value of 0.35 mm; and the width of the residual remainder 7assumes a value of 0.9 mm.

[0059] A method of manufacturing the semiconductor device will now bedescribed.

[0060] First, as shown in FIGS. 4 and 5, a plurality of semiconductorchips 4 are mounted on the surface of the substrate 1. The substrate 1is electrically connected to the semiconductor chips 4 by use of thewires 5.

[0061] Next, the semiconductor chips 4 are collectively sealed withresin, thereby forming the resin-sealed sections 2.

[0062] A plurality of lands 9 (see FIG. 17), which are electricallyconnected to the semiconductor chips 4 and are to be used for mountingthe solder balls, are formed on the back surface of the substrate 1. Thesemiconductor balls 3 are formed on the lands. Here, the lands 9, whichact as terminals for external electrodes, and the solder balls 3 arearranged such that the interval A between the closest terminals of theadjacent semiconductor chips 4 becomes “n” times (where “n” is aninteger greater than 1) the interval B between the terminals provided inone semiconductor chip 4 (or one package 8). For instance, a packagesize is 8 mm×8 mm, and the lands and the solder balls 3 are formed suchthat the interval A assumes a value of 9.6 mm (=0.8 mm×12) and such thatthe interval B assumes a value of 0.8 mm.

[0063] The semiconductor chips 4 are simultaneously subjected to anelectrical test while the chips 4 are mounted on the substrate 1. Asshown in FIG. 5, the electrical test is carried out by use of the testcontact pins 11 arranged in a grid pattern at the same interval as theinterval B (e.g., 0.8 mm) between the semiconductor balls 3.

[0064] After the electrical test has been completed, the slice areas 6formed on the resin-sealed sections 2 and the substrate 1 through use ofa dicer. Here, in order to obtain a desired package size, the sliceareas 6 are sliced twice such that the residual remainder 7 has adesired width of, e.g., 0.9 mm, between the adjacent semiconductor chips4 (or the adjacent packages 8). As a result, the packages 8 areseparated into pieces.

[0065] As has been described, in the first embodiment, commonality hasbeen established in connection with positions of terminals such that theinterval A between the closest terminals (i.e. the lands 9 and thesolder balls 3) of the adjacent semiconductor chips 4 becomes “n” times(“n” is an integer greater than 1) the interval B between terminals ofthe semiconductor chip 4. Hence, so long as there are prepared the testcontact pins 11 of single type, which are arranged in a grid pattern atthe same interval as that between the interval B between terminals ofthe semiconductor chip 4, an electrical test can be carried out throughuse of the same test contact pins 11 even when the size of semiconductorpackages fabricated in the resin-sealed section 2 is varied. Hence,costs for the test tool can be curtailed significantly.

[0066] Moreover, an electrical test can be efficiently carried outduring a period of time required for replacing a test tool with anothertool; that is, without involvement of occurrence of a packagingreplacement loss.

[0067] Since the plurality of packages 8 (or the semiconductor chips 4)can be simultaneously subjected to a test while remaining on thesubstrate, productivity of the electrical test can be improvedconsiderably. In addition, even when a package is miniaturized, therecan be prevented falling of packages, which would otherwise be causedduring the course of an electrical test or during the course oftransport.

[0068] In the embodiment, the residual remainders 7 are left at the timeof separation of the packages 8 into pieces, thereby slicing theresin-sealed sections 2 and the substrate 1 twice. Hence, even when anattempt is made to achieve commonality in connection with the positionsof terminals, a semiconductor device of a desired package size isobtained.

[0069] The embodiment has described a case where a BGA substrate is usedas a substrate for use in manufacturing semiconductor devices; i.e.,packages of BGA types. However, the invention is not limited to such anembodiment and may also be applied to a package of LGA. In such a case,the solder balls 3 must be formed as terminals.

[0070] This invention, when practiced illustratively in the mannerdescribed above, provides the following major effects:

[0071] According to the present invention, commonality has beenestablished between positions of terminals of a semiconductor substrate,thereby curtailing costs for a test tool used for electrical test of thesemiconductor device.

[0072] Further, the present invention is not limited to theseembodiments, but variations and modifications may be made withoutdeparting from the scope of the present invention.

[0073] The entire disclosure of Japanese Patent Application No.2002-200930 filed on Jul. 10, 2002 containing specification, claims,drawings and summary are incorporated herein by reference in itsentirety.

What is claimed is:
 1. A semiconductor device comprising: a plurality of semiconductor chips mounted on a surface of a substrate; sealing resin to be used for collectively sealing said plurality of semiconductor chips; and a plurality of terminals formed on a back surface of said substrate, wherein an interval between said closest terminals of said adjacent semiconductor chips is an integral multiple of the interval between said terminals in said semiconductor chip.
 2. The semiconductor device according to claim 1, wherein two areas to be sliced are formed in said resin located in a position between said adjacent semiconductor chips.
 3. The semiconductor device according to claim 1, wherein said terminals include lands electrically connected to said semiconductor chips.
 4. The semiconductor device according to claim 3, wherein said terminals further include solder balls formed on said lands respectively.
 5. A method of manufacturing a semiconductor device, comprising the steps of: mounting a plurality of semiconductor chips on a surface of a substrate; collectively sealing the plurality of semiconductor chips with resin; forming a plurality of terminals on a back surface of the substrate such that an interval between the closest terminals of the adjacent semiconductor chips is an integral multiple of the interval between the terminals in the semiconductor chip; subjecting the plurality of semiconductor chips to an electrical test; and slicing the resin and the substrate, thereby breaking the semiconductor chips into pieces.
 6. The method for manufacturing a semiconductor device according to claim 5, wherein the electrical test is carried out through use of test contact pins arranged in a grid pattern at an interval identical with that between terminals of the semiconductor chip.
 7. The method for manufacturing a semiconductor device according to claim 5, wherein in said step of slicing the resin and the substrate, areas defined between adjacent semiconductor chips are sliced twice.
 8. The method for manufacturing a semiconductor device according to claim 5, wherein said step of forming the plurality of terminals includes a step of forming a plurality of lands electrically connected to the semiconductor chips.
 9. The method for manufacturing a semiconductor device according to claim 8, wherein said step of forming the plurality of terminals further includes a step of forming solder balls on the plurality of lands respectively. 